ASIC/SoC Functional Design Verification - Hardcover

Mehta

Hardcover

ISBN 10: 3319594176 ISBN 13: 9783319594170

Publisher: Springer, 2017

Synopsis

This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon.  The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail.  He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.

About this title

From the Back Cover:

This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon The author outlines all of the verification sub-fields at a high level, with just enough depth to allow a manager/decision maker or an engineer to grasp the field which can then be pursued in detail with the provided references. He describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.

About the Author:

Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He then worked at Data General, Intel (first Pentium Architecture Verification team) and after a route of couple of startups, worked at Applied Micro and currently at TSMC.

He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs. At TSMC he architected and went into production with two industry standard TSMC ESL Reference Flows that take designs from ESL to RTL while preserving the verification environment for reuse from ESL to RTL.

He holds 14 U.S. Patents in the field of SoC and 3DIC design verification.

He is also the author of Second Edition of the book “SystemVerilog Assertions and Functional Coverage – A comprehensive guide to languages, methodologies and applications”. Springer (June 2016).

Ashok earned an MSEE from University of Missouri.

In his spare time, he is an amateur photographer and likes to play drums on 70’s rock music driving his neighbors up the wall J

About this edition

• Publisher: Springer
• Publication date: 2017
• ISBN 10: 3319594176
• ISBN 13: 9783319594170
• Binding: Hardcover
• Edition number: 1
• Number of pages: 360